Economic success in the semiconductor industry is significantly influenced by further reduction in the minimum feature size which can be produced on a microchip. Reducing the minimum feature size makes it possible to increase the integration density of the electronic components, such as transistors or capacitors on the microchip, and therefore to increase the computation speed of processors and to increase the storage capacity of memory modules. To keep the space required by the components on the chip surface small, in the case of capacitors the depth of the substrate is also exploited. First, a trench is introduced into the wafer. Then, a bottom electrode is produced, for example by those regions of the wafer which adjoin the wall of the trench being doped in order to increase the electrical conductivity. Next, a thin film of a dielectric is applied to the bottom electrode. Finally, the trench is filled with an electrically conductive material to obtain a counterelectrode. This electrode is also known as a top electrode. This arrangement of electrodes and dielectric results in a folded capacitor. For electrode surfaces of the same size, i.e., the same capacitance, it is possible to minimize the lateral extent of the capacitor on the chip surface. Capacitors of this type are also known as deep trench capacitors.
In memory chips, the charged or discharged state of the capacitor corresponds to the two binary states 0 and 1. To allow reliable determination of the charge state of the capacitor and therefore of the information bit stored in the capacitor, the latter needs a certain minimum capacitance. If the capacitance or, in the case of a partially discharged capacitor, the charge drops below this value, the signal disappears in the noise, i.e., the information about the charge state of the capacitor is lost. After writing, the capacitor is discharged by leakage currents which effect a charge compensation between the two electrodes of the capacitor. To prevent information from being lost as a result of the discharging of the capacitor, in the case of DRAMs, the charge state of the capacitor is checked at regular intervals and refreshed as required, i.e., a partially discharged capacitor is charged again until it is restored to its original state. However, there are technical limits imposed on these so-called refresh times, i.e., they cannot be shortened to any desired extent. During the period of the refresh time, therefore, the charge on the capacitor must decrease at most by an extent which is such that it is still possible to reliably determine the charge state. For a given leakage current, therefore, the capacitor has to have a certain minimum charge at the beginning of the refresh time, so that by the end of the refresh time the charge state is still sufficiently well above the noise to allow the information stored in the capacitor to be read out reliably. As the dimensions decrease, the leakage currents increase, since tunneling effects become increasingly important. In order to make it possible to ensure reliable storage of information as miniaturization continues, the capacitor has to have a sufficiently high capacitance. To maintain the desired high capacitance despite the decreasing feature size, a large number of solution approaches are being followed. For example, the surface of the electrodes is provided with a structure in order to make the surface area of the electrodes as large as possible as their length and width decrease. Furthermore, new types of materials are being used. For example, attempts are being made to replace the silicon dioxide which has previously been used as a dielectric by materials with a higher dielectric constant.
To achieve the highest possible capacitance with a given size of a capacitor, it has also been attempted to dope the region of the semiconductor which directly adjoins the dielectric as highly as possible to produce the highest possible charge density in the electrode in the immediate vicinity of the dielectric.
In memory chips, the capacitor is connected to a transistor, which can be used to control the charge state of the capacitor. In the case of deep trench capacitors, the transistor is generally arranged above the capacitor. To make it possible to achieve sufficient electrical insulation between capacitor and transistor, therefore, the top section of the trench, which is adjoined by the transistor, is not doped. Therefore, during the fabrication of deep trench capacitors, to produce the bottom electrode, the trench is filled with a solid form of the dopant, e.g. an arsenic glass, only up to the limit within which the walls of the trench are to be doped. For this purpose, the trench is first of all completely filled with the arsenic glass, and then the filling is etched back to the limit up to which the semiconductor is to be doped. Then, the semiconductor substrate is heated, so that the dopant, for example arsenic ions, diffuse out of the arsenic glass into the semiconductor surrounding it on account of the thermal energy. At the start of the conditioning step, a relatively large quantity of arsenic ions diffuses into the semiconductor, with the number of arsenic ions in the arsenic glass being depleted continuously at the same time. Therefore, during the doping, a gradient is established for the transfer of the arsenic ions into the semiconductor, a maximum concentration of ions which migrate in being established at the start and the concentration of the ions which migrate in decreasing continuously as doping progresses on account of the depletion of the arsenic glass. As the conditioning continues, the arsenic ions diffuse further into the semiconductor, so that a maximum of the arsenic ion concentration is formed as a result of the depletion of the arsenic glass, this maximum gradually being displaced from the wall of the trench into the semiconductor. As a result, the maximum of the charge distribution in the electrode of the completed capacitor is also not arranged directly at the boundary between dielectric and semiconductor. Consequently, the capacitor acquires a lower capacitance than would be possible with a high level of doping at the interface between dielectric and semiconductor. Furthermore, on account of the reduction in the overall size of the capacitor, it is no longer possible for a sufficiently large quantity of arsenic glass to achieve a sufficiently high level of doping of those regions of the semiconductor which adjoin the trench wall to be made available in the interior of the trench.
In order to achieve a sufficiently high level of doping even with small dimensions of the trenches, the dopant can also be introduced into the semiconductor from the gas phase. Since there is always a sufficiently high concentration of the dopant available in the gas phase, a high level of doping of those sections of the semiconductor which form the bottom electrode in the finished capacitor is achieved, it being possible to set a high concentration of the dopant in particular at the interface between semiconductor and dielectric. However, this requires those regions of the semiconductor which are supposed to remain undoped to be covered with a diffusion barrier. Therefore, during the fabrication of deep-trench capacitors, a collar of silicon nitride is built up in the upper section of the trench and then acts as a diffusion barrier during the gas phase doping. For this purpose, the trench can, for example, first be partially filled with polysilicon. Then, a thin film of silicon nitride is deposited on the uncovered walls in the upper section of the trench. The polysilicon is then removed again from the lower section of the trench, so that the wall of the trench is uncovered again in the lower section. These sections, which correspond to the bottom electrode in the finished deep trench capacitor, can then be doped with a dopant from the gas phase. After the doping, the collar made from silicon nitride has to be removed again. However, the procedure needed to remove the silicon nitride collar is difficult. This is because, prior to the processing of a silicon wafer, the top side of the wafer is covered with a thin film of silicon nitride. This imparts a high chemical and mechanical stability to the wafer surface. In the case of chemical mechanical planarization, for example, the top side of the wafer is not removed, so that a planar surface is obtained. During the removal of the silicon nitride collar following the gas phase doping, therefore, the process conditions have to be maintained very accurately. Otherwise, overetching would occur, in which the silicon nitride layer deposited on the surface of the silicon wafer is also removed.
Difficulties with the removal of a temporary protective layer are not only encountered in the example of the fabrication of a deep trench capacitor cited above. For example, it is very difficult to selectively remove sections made from silicon nitride, silicon dioxide or silicon if at least two of these materials are arranged on the surface of a wafer. This constitutes a significant obstacle to the fabrication of large scale integrated electronic components.